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FPGA-based speech encrypting and decrypting embedded system
The Texas A&M team describes an FPGA embedded system design project intended to assess the technology’s suitability for use in real-time, high-performance applications. The test application is a...
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Ensuring reliability through design separation
System designs have traditionally achieved reliability through redundancy, even though this inevitably increases component count, logic size, system power and cost. The article describes the design...
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Device native debug and verification for FPGA
The long loop There is an unstated impression in FPGA design that the process of capturing a design, translating it into a configuration file, and loading that configuration into the silicon consumes...
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Achieving teraflops performance with 28nm FPGAs
Introduction Altera’s 28nm Stratix V FPGAs have a new variable-precision DSP architecture that supports both fixed- and floating-point implementations. However, fully exploiting this with existing...
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Strategic considerations for emerging SoC FPGAs
Semiconductor devices that integrate FPGA fabric, hardened CPU subsystems, and other hardened IP—SoC FPGAs—are poised to proliferate broadly in their usage. SoC FPGAs build upon the decade-long...
View ArticleFPGA prototyping
What is FPGA prototyping? FPGA prototyping is a well-established technique for verifying the functionality and performance of application-specific ICs (ASICs), application-specific standard products...
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Improving ASIC prototyping on multiple FPGAs through better partitioning
ASIC prototyping with FPGAs enables fast system modelling and verification, as well as speeding up the software and firmware development process. Complex ASIC SoC designs have to be partitioned on to...
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Vivado, inside the new Xilinx design suite
The Vivado Design Suite has been released by Xilinx after four years of development and a year of beta testing. It is a highly integrated design environment with a completely new generation of...
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Vivado HLS/AutoESL: Agilent packet engine case study
Gigabit Ethernet is one of the most common interconnect options available to link a workstation or laptop to an FPGA-based embedded platform. This is because of the availability of the hardened...
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How virtual prototyping enabled Altera’s SoC FPGAs
This virtual prototyping case study addresses one of the programmable logic market's newest products. FPGA vendor Altera announced the availability of the first in its line of SoC FGPAs late last year,...
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Strategic considerations for emerging SoC FPGAs
Semiconductor devices that integrate FPGA fabric, hardened CPU subsystems, and other hardened IP—SoC FPGAs—are poised to proliferate broadly in their usage. SoC FPGAs build upon the decade-long...
View ArticleFPGA prototyping
What is FPGA prototyping? FPGA prototyping is a well-established technique for verifying the functionality and performance of application-specific ICs (ASICs), application-specific standard products...
View ArticleClik here to view.
Improving ASIC prototyping on multiple FPGAs through better partitioning
ASIC prototyping with FPGAs enables fast system modelling and verification, as well as speeding up the software and firmware development process. Complex ASIC SoC designs have to be partitioned on to...
View ArticleClik here to view.
Vivado, inside the new Xilinx design suite
The Vivado Design Suite has been released by Xilinx after four years of development and a year of beta testing. It is a highly integrated design environment with a completely new generation of...
View ArticleClik here to view.
Vivado HLS/AutoESL: Agilent packet engine case study
Gigabit Ethernet is one of the most common interconnect options available to link a workstation or laptop to an FPGA-based embedded platform. This is because of the availability of the hardened...
View ArticleClik here to view.
How virtual prototyping enabled Altera’s SoC FPGAs
This virtual prototyping case study addresses one of the programmable logic market’s newest products. FPGA vendor Altera announced the availability of the first in its line of SoC FGPAs late last year,...
View ArticleClik here to view.
High-level synthesis for AI: Part One
Computer vision is a very dynamic part of the artificial intelligence (AI) market. It is attracting massive amounts of funding largely because it targets a very wide range of applications (Figure1)....
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VHDL users also deserve efficient design and verification
Over the past year, this series of eight articles has discussed challenges in writing and debugging design and verification code for semiconductors. The key technology is the integrated development...
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